(a) Field of the Invention
The present invention relates to a wiring board for use in mounting thereon an object to be mounted such as a semiconductor chip or a semiconductor device. More particularly, the present invention relates to a wiring board having a structure in which resin is filled between a semiconductor chip or the like and the wiring board when the semiconductor chip or the like is mounted thereon by flip chip bonding.
Note that, the “wiring board” is hereinafter also referred to as a “semiconductor package” or merely a “package” for the sake of convenience, because it has the function of mounting thereon a semiconductor chip or the like.
(b) Description of the Related Art
In recent years, semiconductor devices have been incorporated into various electronic devices. As electronic devices have been made smaller in size and higher in function, semiconductor devices incorporated into these electronic devices have also been made smaller in size, higher in packaging density, and higher in pin count (higher in terminal count). In addition, the reliability required for these semiconductor devices tends to increase. In general, a semiconductor device has a structure in which a semiconductor chip is mounted on a wiring board (package). As the semiconductor chip to be mounted has been made smaller in size and higher in packaging density, flip chip mounting is widely used as the mounting method.
This flip chip mounting is a mounting method including: first forming bump-shaped electrode terminals (bumps) on a semiconductor chip; and then bonding the electrode terminals of the chip to conductor portions using a conductive material such as solder, the conductor portions being formed on a mounting surface side of the package (i.e. pad portions which are part of a wiring layer exposed from a protection film). Moreover, in order to insulate the bonded portion from the outside thereof, and to enhance its bonding strength, a resin called underfill (such as an epoxy thermosetting resin) is filled into a gap between the package and the chip, and then is fixed by curing.
Since the electrode terminals of the chip and the wiring layer (pad portions) of the wiring board need to be electrically connected in the flip chip mounting, an opening portion for exposing the pad portions is formed in the protection film (typically, a solder resist layer) formed to coat the surface of the wiring board. The arrangement of the pad portions to be formed on the wiring board is determined in accordance with the arrangement of the electrode terminals of a chip to be mounted. Thus, the required shape of the opening portion is also determined in accordance therewith. For example, in the case where electrode terminals of a chip to be mounted are arranged in a peripheral shape (an annular shape along the circumference of the chip), pad portions to be formed on the wiring board are also arranged in the annular shape accordingly. Thus, the opening portion for exposing the pad portions needs to be formed at least in an annular shape in this case.
Thus the required opening portion needs to be formed in the solder resist layer. However, where the edge of the opening portion is positioned inside the mounting area of the chip on the wiring board, the following problems occur. Specifically, in this form, the gap between the solder resist layer and the chip is smaller in vertical dimension than that between the opening portion and the chip. Accordingly, when an underfill resin is filled between the chip and the wiring board, the underfill resin spreads quicker over the solder resist layer than the opening portion by capillary action. As a result, the underfill resin is filled in the circumference of the opening portion quicker than the inside thereof. This causes a void (air bubble) to be formed within the resin filled in the inside of the opening portion. When the void is formed, the connection reliability between the chip and package is lowered because sufficient bonding strength cannot be obtained. In addition, the air inside the void expands due to heat processing after the filling of the resin, which may generate a crack in the underfill resin, and in some cases, may disconnect the electrode terminals of the chip and the wiring layer from each other.
A conceivable way to prevent formation of such a void is to form an opening portion in the solder resist layer in such a manner that the edge of the opening portion is positioned outside the mounting area of the chip (i.e., to form the opening portion larger than the chip size). FIGS. 6A and 6B illustrate an example of the way.
FIG. 6A is a plan view illustrating a state where a resin is filled in a gap formed when a semiconductor chip is mounted on a prior art wiring board (package) for flip chip mounting. FIG. 6B illustrates a cross-sectional structure when viewed along C-C′ line in the plan view of FIG. 6A. In FIGS. 6A and 6B, reference numeral 40 denotes a wiring board. In the wiring board 40, reference numeral 41 denotes a resin substrate constituting a substrate body; reference numeral 42 denotes a wiring layer formed on an outermost surface of the resin substrate 41; reference numeral 44 denotes a solder resist layer which is formed on the resin substrate 41 as a protection film while exposing a pad portion 42P defined at a portion of the wiring layer 42; and reference numeral 46 denotes solder for use in mounting the chip, which is attached to the pad portion 42P. In addition, reference numeral 50 denotes a semiconductor chip mounted on the wiring board 40. In the chip 50, reference numeral 51 denotes a protection film coated on the circuit forming surface side of the chip 50; reference numeral 52 denotes an electrode pad formed to be exposed from the protection film 51; and reference numeral 53 denotes a bump-shaped electrode terminal (bump) bonded to the electrode pad 52.
The electrode terminal (bump) 53 of the chip 50 is bonded to the pad portion 42P on the wiring board 40 via the solder 46 attached to the pad portion 42P. In this manner, the chip 50 is mounted on the wiring board 40 by flip chip bonding. Moreover, an underfill resin 60 is filled between the wiring board 40 and the chip 50 mounted thereon by flip chip bonding.
An opening portion 48 required for exposing the pad portion 42P of the wiring layer 42 provided on the chip mounting surface side is formed in the solder resist layer 44 provided for protecting the surface of the wiring board 40. This opening portion 48 is formed in such a manner that the edge thereof is positioned along and outside the outer shape (rectangle) of the chip 50 (specifically, in such a manner that the opening portion 48 is opened larger than the size of the chip). Moreover, four corners of the opening portion 48 (corner portions R1, R2, R3 and R4) are formed to be opened locally larger, respectively. The reason for widely forming each of the corner portions R1 to R4 is to facilitate injection of the underfill resin 60.
The filling (injection) of the underfill resin 60 is carried out, for example, by moving a nozzle of a dispenser containing a liquid epoxy resin along the sides of the opening portion 48 in the gap between the chip 50 and the wiring board 40. For example, the filling (injection) of the resin into the opening portion 48 is started from any one of the corner portions R1 to R4, and carried out by moving the nozzle of the dispenser to an adjacent corner along the side of the opening portion 48 as indicated by the arrows in FIG. 6A. The example illustrated in FIG. 6A shows the case where the underfill resin 60 is injected along two sides of the opening portion 48 (i.e., the side between the corner portions R1 and R2, and the side between the corner portions R2 and R3). Alternatively, the filling (injection) of the resin may be started from a middle portion of any one of the sides of the opening portion 48, and carried out by moving the nozzle along the corresponding side in the same manner as that in the above case. Hereinafter, the side of the opening portion 48 along which the underfill resin 60 is injected is referred to as a “resin injection side” for the sake of convenience.
As illustrated in FIGS. 6A and 6B, the underfill resin 60 can be quickly spread within a gap between the chip 50 and the wiring board 40 by forming the opening portion 48 larger in size than the chip. Specifically, when the filling of the underfill resin 60 is started from any one of the resin injection sides of the opening portion 48, an inner portion of the opening portion 48 is more likely to be filled with the injected underfill resin 60 by capillary action, and also, air can be released from the opening and corner portions which are opposite to the resin injection side (i.e., downstream side of the flow of the underfill resin 60). Thus the underfill resin 60 can be quickly spread in the gap between the chip 50 and the wiring board 40. As a result, the generation of a void within the underfill resin 60 filled in the opening portion 48 can be prevented.
An example of technique related to the above prior art is described in Japanese unexamined Patent Publication (Kokai) 2005-175113. This publication discloses a printed wiring board for flip chip mounting. This printed wiring board includes: a substrate body on which an IC chip is mounted and a board conductor connected to an electrode of the IC chip is formed; and an insulating protection film which is formed on the substrate body and which has an opening portion formed therein at a mounting position of the IC chip. In this printed wiring board, a resin is filled between the IC chip and the substrate body in the state where the IC chip is mounted on the substrate body; the distance between each side of the outer shape of the IC chip and the opening edge of the insulating protection film is selected to be a predetermined value; and all of the four corners of the opening portion are widely opened.
As described above, in the prior art semiconductor package (FIG. 6A), the opening portion is formed larger in size than the chip in the solder resist layer provided for protecting the package. Thereby, when an underfill resin is filled between the chip and the package after mounting the chip on the package, the generation of a void within the filled resin is prevented. Such a shape of the opening portion is effective in preventing the generation of a void. However, there is a disadvantage in that a fillet of the underfill resin 60 (portion surrounded by a broken line DF) is not sufficiently formed as schematically illustrated in the cross-sectional view of FIG. 6B (cross-sectional view of the vicinity of the corner portion R4 in the opening portion 48).
Specifically, as illustrated in FIG. 6A, the resin injection sides along which the underfill resin 60 is injected (the sides of the opening portion 48 illustrated with arrows) and the opposite sides (downstream side of the flow of the underfill resin 60) are formed in the same shape. Thus, it is highly possible that the underfill resin 60 does not sufficiently flow to the opposite sides, in particular, to the corner portion R4. When the underfill resin 60 does not sufficiently flow thereto, the opening portion of the corner portion R4 fails to be sufficiently filled with the resin 60. As a result, the portion not coated with the underfill resin 60 (portion where the resin substrate 41 is exposed) is formed as illustrated in FIG. 6B. In the illustrated example, since the exposed portion corresponds to an insulating layer of the resin substrate 41, there is no particular problem in operation as the package. However, the presence of such area depreciates the appearance of the package. Namely, the insufficient fillet of the underfill resin 60 adversely affects outer appearance.
In addition, although not particularly illustrated, some packages have a wiring or the like formed in the locally widely opened corner portion. In this type of package, when the corner portion is not sufficiently filled with the resin as exemplified in FIG. 6, there occurs a problem in terms of insulation properties because the wiring or the like is exposed.
These problems are not peculiar to a semiconductor package represented by a ball grid array (BGA), a land grid array (LGA) or a pin grid array (PGA), and may possibly occur likewise in a flip chip mounting type package having a structure in which different packages are stacked on each other (also referred to as “package-on-package”). Specifically, taking into consideration the case where: first, a semiconductor chip is mounted on a lower package (wiring board) by flip chip mounting; then, bumps formed on a mounting surface side of an upper package are bonded, via solder or the like, to conductor portions (pad portions) formed in a peripheral region of the chip on the lower package; and an underfill resin is filled between the upper and lower packages, the above problem may possibly occur likewise.